Satwinder Singh, Infineon 2014-07-22T10:41:22+00:00

Name:Satwinder Singh
Designation:Senior Staff Engineer in Verification
Title:Using Certitude for Relative Functional Qualification of a Re-usable Testbench

Abstract : The presentation discusses a novel use of Certitude tool to ensure the quality of a reusable testbench does not deteriorate across projects. The flow described in the presentation reuses Certitude results to ensure that adding functionality for reuse doesn’t affect the testbench’s existing functions, in a run that takes about one hour (in contrast to our standard Certitude run taking about 3 weeks), enabling us to run these checks frequently. Since we reuse sign-off Certitude results from a completed project, the flow also makes it possible to run high coverage Certitude regressions early in a project. The frequency & quality of the runs ensure that bugs introduced in the testbench are found quickly, simplifying debug and reducing the risk of finding critical bugs late in the project. The flow was deployed across a significant change to our verification environment and found multiple bugs including 3 serious ones.

Biography: I have been with Infineon for the last 4 years working on TriCore CPU Verification primarily responsible for Random Architectural Test Generation (ISG) for the TriCore CPU. Lately I have also been involved in Functional Qualification of the TriCore CPU Verification Environment and devising methods to reduce the cost of Functional Qualification. Overall, I have a number of years of experience and expertise in verifying complex CPU architectures/micro-architectures, having worked previously on the verification of AMD(x86) &IBM(z-Series Server) processors. I have a BEng in Electronics & Communication Engineering from University of Delhi.

DVClub Presentation                                    The recording is unavailable due to a technical problem


The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.