Yogish Sekhar, Dialog Semiconductors 2014-07-22T10:42:01+00:00

Name:Yogish Sekhar
Designation:Verification Specialist
Title:Measuring the Effectiveness of Verification Environments

Abstract : Shrinking transistors sizes means more complex design is squeezed into the same area that was used a product generation earlier. The world is aware of Moore’s law for design; but it is more applicable to the verification space today as verification complexity has increased exponentially. There are multitudes of tools (i.e. simulators, methodologies) that tell us how we need to verify our designs and various different metrics that tell us what we have verified.

In a world where “only the paranoid survive”, can we really say that every possible scenario has been covered and verified? NO. We only can understand the risks we are taking and solutions to mitigate those risks. Any tool/framework that helps in identifying these risks early on in the verification cycle, will have a huge impact on the design/product either becoming a revenue generator or being assigned to the dump!

Biography: Yogish Sekhar has over 13 years of Experience of which 10 years in Digital Verification. He has a masters’ degree from University of Edinburgh and has worked in Intel, Wipro in India and Broadcom, ARM here in the UK before taking up his current position at Dialog Semiconductor.

DVClub Presentation                                                                                                                                Video Presentation

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.