Gaurav Jain, Freescale Semiconductor Pvt Ltd 2015-01-06T11:08:00+00:00


Name: Gaurav Jain
Designation: Staff Design Engineer
Title: Assertions: A Smart Path to Low Power Verification of Complex SoCs

Abstract:  Low Power SoC designs implementing multiple low power design techniques like fine grained clock gating, power shut off involving multiple low power domains, body or well biasing, dynamic frequency and voltage scaling, significantly increases the scope and target areas for SoC Verification. The dynamic simulation driven verification approach is cycle time and debug effort intensive, when it comes to catching low power integration and design issues. Assertions targeted towards low power verification can provide a smart path to reduce cycle time and to help in catching issues early in verification by clearly highlighting type and source of the issue. The assertions can provide useful coverage information along with system level cross coverage on key signals to measure verification completeness. They can also be re-used by other projects by creating template properties. This paper presents a case study on deployment of System Verilog Low power assertions along with CPF enabled dynamic simulations to verify a Next Generation Low Power SoC. Multiple assertions categories were deployed to target verification of low power design features, Integration of Macro models, sequencing and connectivity of critical control signals and to prove the clocking and reset schemes in each device mode. We found several low power design issues related to connectivity, protocol sequence and functional behaviour of control signals like power down signals. The Assertion based verification approach gave a great ROI with savings on cycle and debug time which helped in robust and timely verification of low power intent of our SoC with high confidence.


Biography:  Gaurav Jain is Staff Design Engineer at Freescale Semiconductors, India.  He has nine years of experience and expertise in SoC& IP Verification, Low Power Verification and Pre-Silicon Validation domains.  Gaurav has experience on Industry standard protocols like AMBA AHB, AXI, MIPI, ENET and DDR.  Gaurav holds a bachelor’s degree in Electronics Engineering from IIT-BHU, Varanasi, India.


View the Presentation Materials:
The presentation and recording will be made available following approval from

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.