Venkatesh Vasudevan, Test and Verification Solutions Ltd (T&VS) 2015-03-05T16:49:38+00:00


Name:Venkatesh Vasudevan
Designation:Project Lead – SystemC Modeling
Title:Performance Modeling using SystemC & TLM 2.0

Approximately Timed (AT) Modeling can be used for Performance Modeling of Designs. AT is an abstraction level where timing points are introduced and are represented by phases. The TLM 2.0 standard defines three schemes in general. These are single phase, two phase and four phase. These schemes can be extended by definition of custom phases.

T&VS has been involved in performance modeling of System-on-Chip (SoC) blocks. Models are being developed for blocks such as LPDDR4 Memory Controller, AXI4 bus etc. Custom phases have been introduced where applicable and the TLM 2.0 Generic Payload is used as much as possible.

Venkatesh Vasudevan has been with T&VS for the past 2 months as Project Lead – SystemC. At T&VS he is in-charge of SystemC and TLM 2.0 based development. Prior to joining T&VS, he held senior positions at SPEL Semiconductor Ltd, Cognizant Technology Solutions, Conexant Systems Inc and Siemens Information Systems Ltd.
He has been involved in the Chip Design & Verification Industry for the past 10 years and holds a PhD in Fault Tolerant Digital Design from the University of Queensland, Australia.


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