Ziyad Hanna, Jasper 2014-07-22T10:44:15+00:00

Name:Ziyad Hanna
Designation:Senior VP of R&D, Chief Architect and General Manager (Jasper Israel)
Title:Integrating Formal and Simulation Results to See the Full Verification Picture

Abstract : Advanced Formal Technology has grown to address large SOCs and many of the more difficult design and verification challenges. Thus, it’s critical for users to be able to seamlessly integrate results from formal methods with their simulation results to generate comprehensive snapshots and trend analyses of their progress. In this presentation we highlight a use case study on design coverage verification. We will also describe how formal coverage metrics, even for “bounded proofs”, can give users the information they need to accelerate the coverage closure process.

Biography : Ziyad Hanna is responsible for advancing the company’s breakthroughs in formal verification technology, core engines and system architecture. Ziyad has over 20 years of industry experience. Prior to joining Jasper, Ziyad was Intel senior principal engineer and the main leader of the Formal Technology Research and Development Group in the Design and Technology Solutions division at Intel Haifa. While at Intel, Ziyad was instrumental in the development of several generations of formal verification systems used on almost all Intel microprocessor designs since early 1990s. A senior IEEE member, Ziyad has been active in the area of formal verification for over 17 years, and has mentored many research projects with academia and served in various international conferences including SAT, ICCAD, DAC and ICCD. He has published more than 25 articles the formal area and holds 8 patents. He received both his B.Sc. and M.S. degrees in computer science at Tel-Aviv University. He received his Ph.D with research in “Abstract Modelling and Formal Verification of Microprocessors” at the Computing Laboratory of Oxford University.

DVClub Presentation                                                                                                                          Video Presentation

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.