|Designation:||Solution Architect Verification|
|Title:||UVM1.2: What’s Now and What’s Next|
Abstract: Since the first release of UVM in early 2011 it has been a tremendous success throughout the verification industry. Today it’s the defacto standard for any functional verification activity. A key point for UVM is that a lot of focus is being put upon backward compatibility with any change applied to the UVM core library. Lots of enhancements to the library have been deferred in order to avoid migration problems. The next version of UVM labelled 1.2 is the first release since the initial release of UVM-1.0 which will have new facilities, enhancements and capabilities NOT API compatible with the older UVM versions. The presentation will help you to better understand the differences between UVM12/UVM10 and the estimate effort/path to migrate to UVM-1.2. In addition we will be outlining core simulator debug capabilities targeting UVM facilities enabling a much faster debug and analysis of UVM based test cases.
Biography: Uwe works as a Solution Architect for the Cadence Verification Division with almost 20 years experience in design, implementation and verification of complex chip designs in various companies. Over the years he has been exposed to various tools in the analog and digital simulation world, languages (VHDL, SystemVerilog, SystemC, Specman/e), programming concepts (AOP,OOP) and methodologies (eRM,OVM,UVM).
He is currently focusing upon UVM-SystemVerilog and is owning the technical activities related to UVM-SV inside Cadence. He holds a “Dipl.-Ing” (the german equivalent of a Master’s Degree) in Information Technology from the Dresden University of Technology.
View the Presentation Materials: