DVClub on 9 September 20132017-05-17T10:39:22+00:00

SystemVerilog and UVM Update

AGENDA

11.30Arrival and Networking
12.00Introduction by Dr Michael Bartley, T&VS
12.05Adam Sherer, Accellera UVM Working Group Secretary,
12.25Steve Holloway, Dialog Semiconductor, Changes to the Register Abstraction Layer
12.50Alan Fitch, Doulos, SystemVerilog Scheduling Semantics
13.10 Francois Cerisier, T&VS, Advanced scoreboarding techniques using UVM
13.30Close and Networking

Note : Above timings are in BST