|Designation:||Principal Member, Technical Staff|
|Title:||SystemVerilog Scheduling Semantics|
Abstract : The 2009 revision of the IEEE Standard for SystemVerilog included a number of changes to the scheduling semantics of SystemVerilog which can impact users. We provide a brief tutorial on the SystemVerilog scheduler, including the impact of the changes to the 2009 standard and what you need to know to avoid the pitfalls.
Biography : Alan Fitch has a BSc. (Hons) degree in Electronic Engineering, and started his career at Philips Semiconductors (now NXP) working on digital filtering for cellular radio; followed by work on many other topics from digital design using VHDL to specification of Zero-IF radio receivers for digital telephony.
After a brief spell teaching at a further education college in the UK, he joined the global language and
methodology training company Doulos in 1998. At Doulos he has continued his involvement in ASIC
and FPGA design and modeling through consultancy work, but has also been greatly involved in
developing and delivering HDL-related training classes and reference material. He has a particular
specialization in SystemC/TLM2 and VHDL, and also teaches SystemVerilog/UVM, PSL, and Verilog.
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