Making Verification Debug More Efficient
Friday, 26 September 2014
Agenda
| 14.00 | Arrival and Networking |
| 14.10 | Welcome |
| 14.15 | Test and Verification Solutions, Mike Bartley (CEO and Founder) Title: Improving Debug – Our biggest challenge? Presentation Language: English |
| 14.25 | Real Intent, Ramesh Dewangan (Vice President) Title: Shortening Debug with New Methods in Static Verification Presentation Language: English |
| 14.55 | Solvertec GmbH, Daniel Große (CEO) Title: Circuit Design: Slip Schedule or Automate Debug Presentation Language: English |
| 15.25 | Mentor Graphics, Joe Hupcey Title: High-Throughput Debug Recommendations: Making Verification Debug More Efficient Presentation Language: English |
| 15.55 | Coffee Break (5 minutes) |
| 16.00 | Cadence, Chen Liang (Principal Solutions Engineer) Title: Revolutionary Debug Techniques to Improve Verification Productivity Presentation Language: Chinese |
| 16.30 | Synopsys, Rich Chang (Product Marketing Manager) Title: Complete SoC Debug Solution – From HW to SW debugging approaches Presentation Language: Chinese |
| 17.00 | ARM, Jing Wang (Senior Applications Engineer) Title: The Current CoreSign System for SW Debugging in an ARM-based SoC Presentation Language: Chinese |
| 17.30 | Local Q&A Session (5 minutes) |
| 17.35 | Close and Networking |