DVClub Shanghai- Friday, 26 September 2014 2014-10-08T06:59:12+00:00

Making Verification Debug More Efficient

Friday, 26 September 2014


14.00Arrival and Networking
14.15Test and Verification Solutions, Mike Bartley (CEO and Founder)
Title: Improving Debug – Our biggest challenge?
Presentation Language: English
14.25Real Intent, Ramesh Dewangan (Vice President)
Title: Shortening Debug with New Methods in Static Verification
Presentation Language: English
14.55Solvertec GmbH, Daniel Große (CEO)
Title: Circuit Design: Slip Schedule or Automate Debug
Presentation Language: English
15.25Mentor Graphics, Joe Hupcey
Title: High-Throughput Debug Recommendations: Making Verification Debug More Efficient
Presentation Language: English
15.55Coffee Break (5 minutes)
16.00Cadence, Chen Liang (Principal Solutions Engineer)
Title: Revolutionary Debug Techniques to Improve Verification Productivity
Presentation Language: Chinese
16.30Synopsys, Rich Chang (Product Marketing Manager)
Title: Complete SoC Debug Solution – From HW to SW debugging approaches
Presentation Language: Chinese
17.00ARM, Jing Wang (Senior Applications Engineer)
Title: The Current CoreSign System for SW Debugging in an ARM-based SoC
Presentation Language: Chinese
17.30Local Q&A Session (5 minutes)
17.35Close and Networking
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.