|Title:||Circuit Design: Slip Schedule or Automate Debug|
When verification fails, the (verification) engineers have to manually find the root cause of the bug based on wave form viewers and visualization tools. Hence, the localization and fixing of bugs (debugging) has become the biggest bottleneck in the design of digital integrated circuits.
This presentation will explain the tool Debug!t, a solution to automate debugging of digital RTL designs. Debug!t performs a root cause analysis of the sources of a design error. It pinpoints to those lines where corrections are possible. Thus Debug!t benefits to meet the design schedule and to get chips designs faster to the market.
Daniel Grobe is responsible for leading solvertec’s team to successfully bringing the company’s pioneering technology to the mainstream design debug market. He has over 10 years of experience in hardware verification and debugging. Daniel published more than 50 peer-reviewed papers and served in several program committees. He received his Diploma degree in computer science from the Albert-Ludwigs University, Freiburg, Germany, and holds a summa cum laude Dr.-Ing. degree from the University of Bremen, Germany.
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DVClub Shanghai Presentation