Ramesh Dewangan, Real Intent 2015-04-08T15:17:03+00:00

real_intent

Name: Ramesh Dewangan
Designation: Vice President of Application Engineering
Title: Shortening Debug with New Methods in Static Verification

Abstract:
Not only today’s SoC pack more transistors with lower nodes to meet the performance and capacity demands, they also have high degree of re-use and integration of multiple IPs. Not only do IPs need to be verified with a rigorous methodology, there must be a sound methodology for the IPs to be integrated smoothly in the SoCs. Additionally, you have significantly more design aspects that need analysis, including X-propagation, clock domain crossings, reset integrity, deadcodes, deadlocked FSMs, and low-power budgets.

These challenges have created a huge stress in the current functional verification methodologies, which rely primarily on dynamic verification. The simulation debug cycle times are getting unpredictable and very long. The static verification techniques are emerging to fill the gaps to reduce verification cycle time significantly.

In this presentation we’ll provide overview of new static verification techniques that targets specific problem domains like clock domain crossing, reset optimization, X-optimism/pessimism, FSM integrity and so on, which improve overall verification methodology in ways we had not imagined before.

Biography:
Ramesh brings 25+ years of experience in engineering, customer management, product management and marketing to Real Intent. Prior to joining Real Intent, he led the product marketing of the core product suite related to RTL design at Atrenta. He began his career at Texas Instruments, where he managed an international design automation operation. At Synopsys, he managed a SEMATECH funded engineering alliance, and an international CAE team for the design implementation products. His career has spanned Cadence and Tera Systems where he managed key products related to formal verification, physical design and timing analysis. Ramesh holds an MBA degree from the Walter A. Haas School of Business, University of California; and a bachelor of technology degree in electronics from the National Institute of Technology Karnataka, India.

View the Presentation Materials:
Video Presentation

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.