Ramesh Dewangan, Real Intent 2015-04-08T15:17:03+00:00


Name:Ramesh Dewangan
Designation:Vice President of Application Engineering
Title:Shortening Debug with New Methods in Static Verification

Not only today’s SoC pack more transistors with lower nodes to meet the performance and capacity demands, they also have high degree of re-use and integration of multiple IPs. Not only do IPs need to be verified with a rigorous methodology, there must be a sound methodology for the IPs to be integrated smoothly in the SoCs. Additionally, you have significantly more design aspects that need analysis, including X-propagation, clock domain crossings, reset integrity, deadcodes, deadlocked FSMs, and low-power budgets.

These challenges have created a huge stress in the current functional verification methodologies, which rely primarily on dynamic verification. The simulation debug cycle times are getting unpredictable and very long. The static verification techniques are emerging to fill the gaps to reduce verification cycle time significantly.

In this presentation we’ll provide overview of new static verification techniques that targets specific problem domains like clock domain crossing, reset optimization, X-optimism/pessimism, FSM integrity and so on, which improve overall verification methodology in ways we had not imagined before.

Ramesh brings 25+ years of experience in engineering, customer management, product management and marketing to Real Intent. Prior to joining Real Intent, he led the product marketing of the core product suite related to RTL design at Atrenta. He began his career at Texas Instruments, where he managed an international design automation operation. At Synopsys, he managed a SEMATECH funded engineering alliance, and an international CAE team for the design implementation products. His career has spanned Cadence and Tera Systems where he managed key products related to formal verification, physical design and timing analysis. Ramesh holds an MBA degree from the Walter A. Haas School of Business, University of California; and a bachelor of technology degree in electronics from the National Institute of Technology Karnataka, India.

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