|Title:||Formal Verification: As I know it|
Abstract: Formal Verification (FV) is one of the important tools in the Design Verification (DV) engg. arsenal. When used effectively it can help the DV engg. to improve quality and productivity. In this talk I will share my experiences and learning’s on FV usage. Specifically, I will touch upon how I got started, areas I have found FV to be effective, some real world examples and finally how FV is going to be used in future.
Biography: Sudhakar is a Technical lead in MCU division at Texas Instruments, currently focusing on Analog integration. He has earlier worked on IP verification, SoC verification, Emulation, Prototyping, Silicon Validation and Leading teams. He has six publications and three patents on verification and micro-architecture. He holds MSc degree from IISc, Bangalore and BE from PSG College of Technology, Coimbatore.
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