Bring IP Verification Closure to SoC 2015-12-03T11:55:27+00:00
Conference:DVClub Europe – December 2015 (click here to see full programme)
Speaker:Gaurav Gupta (Staff Design Engineer)
Organisation:Freescale Semiconductor Inc.
Presentation Title:Bring IP verification closure to SoC, Scalable Methods to Bridge the Gap between IP and SoC Verification
Abstract:To cater to exponentially growing complexity and ever so shirking ‘Time to Market’, we need to find better ways to achieve our verification goals faster. Distinction between IP and SoC verification is getting obscured as dynamics of verification is shifting to a ‘Sub-System’ containing multiple IPs working together.

There is a clear need to make SoC verification and IP verification more ’inter-reusable’ in-order to mitigate not just the issues in modelling of environments around Standalone IPs versus actual SoC/Sub-System but also to empower system level verification environment with scalable and re-usable methodology which defines guidelines about how to handle and manage verification problems efficiently in structured manner.

It would be desirable to not just be able to port stimulus from IP verification environment to a SoC verification environment but to have SoC environment an extension of the IP verification environment.

  • Stimulus Portability from IP verification environment to a sub-system/SoC environment which is controlled by CPU(s)
  • Eliminates duplication by removing requirement of developing ‘C’ patterns to guide CPU(s)
  • Enables Testbench controlled processor execution
Speaker Bio:Gaurav Gupta is a Staff Design Engineer with the Automotive Microcontroller Product Group at Freescale Semiconductor Inc. He has 10 years of experience spanning across organizations like Synopsys, Wipro and Freescale. He has worked in the area of Functional and Formal verification, and development of Assertion IPs for protocols such as AXI and OCP.His primary responsibilities include verification of complex IPs in the area of High Speed Serial Interfaces, and Image signal processing IPs and sub-systems for ADAS. Gaurav has authored multiple papers in the domain of Functional and Formal verification.

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