|Conference:||DVClub Europe – December 2015 (click here to see full programme)|
|Speaker:||Adiel Khan (Senior Staff Engineer, Verification Group Business Unit.)|
|Presentation Title:||Reaching Coverage Should be Science Not Art.|
|Abstract:||“Coverage Closure” is the process used to reach 100% of your coverage goals. In a directed test methodology, it is simply the process of writing all of the testcases outlined in the verification plan.
For RTL-Code coverage this is ensuring all lines and conditions of code have been executed. In a constrained-random methodology, it is the process of adding constraints, defining scenarios or writing directed tests to hit the uncovered areas in your functional and structural coverage model. In the latter case, it is a process that is time-consuming and challenging: you must reverse-engineer the design and verification environment to determine why specific stimulus must be generated to hit those uncovered areas.
Something that is challenging and time-consuming is an ideal candidate for automation. In this case, the Holy Grail is the automation of the feedback loop between the coverage metrics and the required stimulus. The challenge in automating that loop is correlating those metrics with the input constraints, rather than leaving the engineer to draw out and hypothesize on possible ways to reach that coverage metric.
|Speaker Bio:||Adiel has spent over 15 years entrenched in Verification both in and out of EDA. In that time he has built his own methodologies and worked on eRM/VMM/UVM development. Being the main Synopsys interface to UVM he has taken it to the AMS space in authoring UVM-AMS libraries, and taken it to emulation space defining the main principles for UVM-Acceleration.
Working with strategic partners Adiel helps identify where EDA can really bring value to verification projects whether it be updating existing technology or exploring new opportunities. Having a holistic role on the Verification Compiler technologies allows him to focus on where Verification Gaps exist in real-world verification projects.
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