|Conference:||DVClub Europe – May 2016 (click here to see full programme)|
|Presentation Title:||Automatic, Validated Debug of Regression Failures –|
|Abstract:||The number of test failures to debug is larger than ever. This is due to 3 reasons: 1) larger ASIC projects, 2) constrained random testing and 3) automatic testing. Basically, in order verify the larger ASIC’s we run more tests more frequently than ever before. The result is that debugging is now by far the largest of all the verification tasks in an ASIC project.
However, today it is possible to automate debugging, but in order for any automation to be useful in a live project the results have to be robust. This can be achieved by validation of the debug analysis: if the debug analysis was correct it should be possible to make the failing test pass by automatically modifying the code. Only if the test failure can be made to pass has the debug analysis been validated. Here we present how we achieved automatic, validated debug of regression failures.
|Speaker Bio:||Daniel Hansson has more than 15 years experience as an ASIC designer and project manager from Ericsson, Texas Instruments and ARC cores. The last 6 years he has spent on PinDown, the automatic debug tool for regression testing.|
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