Automatic, Validated Debug of Regression Failures 2016-05-26T02:52:24+00:00
Conference: DVClub Europe – May 2016 (click here to see full programme)
Speaker: Daniel Hansson
Organisation: Verifyter
Presentation Title: Automatic, Validated Debug of Regression Failures
Abstract: The number of test failures to debug is larger than ever. This is due to 3 reasons: 1) larger ASIC projects, 2) constrained random testing and 3) automatic testing. Basically, in order verify the larger ASIC’s we run more tests more frequently than ever before. The result is that debugging is now by far the largest of all the verification tasks in an ASIC project.

However, today it is possible to automate debugging, but in order for any automation to be useful in a live project the results have to be robust. This can be achieved by validation of the debug analysis: if the debug analysis was correct it should be possible to make the failing test pass by automatically modifying the code. Only if the test failure can be made to pass has the debug analysis been validated. Here we present how we achieved automatic, validated debug of regression failures.

  • Debugging is now by far the largest verification task in an ASIC project
  • Automation of debug is possible, but requires validation for robust results
  • We present our solution for Automatic, Validated Debug of regression failures
Speaker Bio: Daniel Hansson has more than 15 years experience as an ASIC designer and project manager from Ericsson, Texas Instruments and ARC cores. The last 6 years he has spent on PinDown, the automatic debug tool for regression testing.

View the Presentation Materials:

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.