|Conference:||DVClub Europe – May 2016 (click here to see full programme)|
|Speaker:||Ian Gibbins & Krzysztof Szczur|
|Presentation Title:||Debug with Emulation – Revealing what’s not Visible with Simulation|
|Abstract:||Emulation is becoming increasingly popular and being used much earlier than traditional FPGA prototyping in the verification process. For example, Simulation acceleration is being considered as soon as major blocks of SoC are available. For this reason, advanced debugging capabilities are required to trace issues and find bugs while running emulation instead of running pure HDL simulation. The result is the advantage of revealing issues that would not be visible purely with weeks of HDL simulation.
|Speaker Bio:||Ian is a Chartered Engineer (MIET) with 30 years of experience in ASIC and FPGA design. Initially working in R&D and later consulting in mobile communications, he has spent 15 years in customer sales and support. Ian joined FirstEDA in 2006, where he has technical responsibility for a broad range of verification and validation solutions, including Aldec’s class-leading portfolio.
Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES™, Aldec’s FPGA-based co-simulation and emulation technology. He has worked in the fields of HDL IP-cores verification, testbench automation and design verification for DO-254 compliance. As a Technical Support Engineer and now Manager, Krzysztof has practical experience and a deep understanding of co-simulation, emulation and prototyping as well as hardware tools training skills.
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