Hardware-Software Debug for Portable Stimulus Test Cases 2016-05-24T12:42:32+00:00
Conference:DVClub Europe – May 2016 (click here to see full programme)
Speaker:Adnan Hamid
Organisation:Breker Verification Systems
Presentation Title:Hardware-Software Debug for Portable Stimulus Test Cases
Abstract:The upcoming portable stimulus standard from Accellera will define an abstract model of verification intent from which test cases can be generated for a variety of platforms. These test cases and any tools implementing the standard must handle more than just stimulus: results checking, coverage, and debug support are also needed. This talk focuses on a proven approach to enable faster and easier debug of generated test cases portable across multiple platforms. Since these test cases run on embedded processors, they are a form of hardware-software verification and the debug methodology must correlate activity in the test cases and in the design being verified.

  • Success with portable stimulus requires effective debug
  • Debugging portable test cases involves both hardware and software
  • Correlation is critical to understand embedded test cases
Speaker Bio:Adnan Hamid is the founder CEO of Breker Verification Systems and the inventor of its core technology. He has over 20 years of experience in functional verification automation. Prior to Breker, he managed AMD’s System Logic Division, and led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor. In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors. He holds nine patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

View the Presentation Materials:

  • At the request of the speaker Presentation Slides will not be available post-event.
  • At the request of the speaker recording Slides will not be available post-event.
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.