Speaker: Adnan Hamid, Breker Verification Systems, Inc. 2016-01-28T09:54:48+00:00
Conference:DVClub Europe 2015 (click here to see full programme)
Speaker:Adnan Hamid, Co-Founder and CTO
Organisation:Breker Verification Systems, Inc.
Presentation Title:Cache Coherency Verification with Vertical and Horizontal Portable Stimulus
Abstract:The industry is buzzing over the need for portable stimulus and tests, including an active Accellera working group looking to standardize this area. Portability must include vertical reuse from IP block to subsystem to SoC, and horizontal reuse from ESL model to RTL simulation to hardware platforms, including silicon in the bring-up lab.This talk uses cache coherency verification, a critical need in today’s multiprocessor systems, as an example for portable stimulus. Most cache coherency verification occurs with generated C test Cases that run on embedded processors at every phase of the project, from ESL models through actual silicon. These test cases can be tuned for each platform, enabling true horizontal verification reuse. For IP blocks and subsystems that do not include the processors, test cases can be generated in the form of Transactions for bus models within a UVM simulation testbench. This enables true vertical reuse as well.

  • Truly portable stimulus must Support vertical and horizontal reuse
  • Cache coherency verification via generated C test cases is horizontally reusable
  • Cache coherency verification is also vertically reusable from Transactions on bus models to C test cases running on multiple embedded processors
BiographyAdnan Hamid is co-founder and CTO of Breker Verification Systems, focusing on SoC verification. His background includes managing AMD’s System Logic Division and serving as an expert in system-level verification at Cadence. Adnan received BS degrees in Electrical Engineering and Computer Science from Princeton, and an MBA from UT- Austin.

View the Presentation Materials:

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.