|Conference:||DVCLUB Europe: SAFETY (Nov 2016)|
|Presentation Title:||Formal Fault Injection|
|Abstract:||Safety mechanisms are one of the most critical areas of ISO-26262 compliant automotive designs and their architecture and quality are a key differentiator for various IC providers. This implies that they should be verified as rigorously as possible, and their efficiency in detecting and correcting faults thoroughly and accurately analyzed. While verifying a sample of possible use cases might be sufficient for less critical areas, safety mechanisms require more rigorous means.
Formal Fault Injection is a verification technique used in safety critical automotive devices as well as other high reliability applications. In our formal fault injection approach, we use the sequential equivalence checking technology on the DUV’s HDL applied on two copies of the DUV: one copy for fault injection another that is used as reference when checking for the impact of a fault injection. Fault injection consists of changing the value of a selected design signal at an arbitrary time point for a given period of time and checking the effect of this “change” at some other design observation elements. If observation points get values different to their reference values, then the fault is propagated to the observation point and the fault has been not captured by the safety mechanism.
The tool not only provides pass/fail information it also collects fault metrics for the DUV.
|Speaker Bio:||Mark has been involved in the design and verification of complex SoCs for over 20 years.
He has worked as an applications engineer with Mentor Graphics for the past 15 years, focusing primarily on the areas of static and low power verification.
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