Methodologies For Rigorous Safety Verification 2017-10-23T13:51:07+00:00

DVClub Europe Meeting – November 2017

Methodologies for Rigorous Safety Verification


Customising APIS IQ Software for ISO26262 Safety Analysis – Closing the Gap From Concept to Verification

Speaker:Krishnapriya Chakiat Ramamoorthy, Lead Concept Engineer, Automotive Embedded Flash Systems, Infineon Technologies UK Ltd.
Conference:DVCLUB Europe: 28 November 2017
Abstract:Complex designs achieve ISO26262 via the introduction of Safety Mechanisms to protect against random hardware faults that can cause a violation of a Safety Goal. The challenge is in performing a comprehensive safety analysis of the design, and proving the completeness of the analysis in an efficient manner.

This presentation will show how APIS IQ features (until now used for systematic failure mode analysis) are innovatively used to identify the potential Random Hardware Faults which can disrupt the function of a design, leading to a failure to meet a Safety Goal.

Finally, the presentation provides a suggestion on how to link this conceptual analysis to design and verification plans, thus closing the gap between architecture and verification.

  • Systematic collection of potential failure modes
  • Coverage analysis of Safety Mechanisms w.r.t failure modes
  • Hierarchical presentation of results to facilitate effective analysis
    Thereby achieving an effective (high quality) analysis in an efficient and comprehensive manner.
Speaker Bio:The speaker has extensive experience in several areas of semiconductor development, including verification, design and concept or system engineering. In her current role, she leads the activities on the architecture, specification and safety analysis of the automotive embedded flash systems, working with multiple teams spanning different countries.
Register for FREE

Event Organiser


DVCLUB Europe is made possible through the generosity of our sponsors.

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.