DVClub Europe Meeting – November 2017
Methodologies for Rigorous Safety Verification
How Formal Reduces Fault Analysis for ISO 26262 Safety Verification
|Speaker:||Bryan Ramierz, Design & Verification Product Marketing Manager, Mentor a Siemens Business|
|Conference:||DVCLUB Europe: 28 November 2017|
|Abstract:||The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult because evaluating every possible fault is impractical on the size of today’s designs.|
Formal verification tools have an advantage over other approaches because formal tools have the unique ability to trace cones of influence and eliminate large numbers of irrelevant faults in a process known as fault pruning. With a significantly reduced fault list, fault analysis can be performed exhaustively with formal techniques like sequential logic equivalency checking (SLEC), or coupled together with fault simulation and emulation for checking software based safety mechanisms. Formal tools provide unique capabilities that are essential for any automotive functional safety flow.
|Speaker Bio:||Bryan Ramirez is the Product Manager for Strategic Markets at Mentor, A Siemens Business, focusing on helping customers evolve their verification practices. Bryan joined Mentor in February 2015 and his role at Mentor builds upon his 15+ years of experience working with FPGAs and advanced verification. Bryan spent 12 years at Xilinx as a verification lead and engineering manager doing IP development for advanced protocols like PCIe, Serial RapidIO and memory controllers. Following Xilinx, Bryan was Director of Engineering at a startup building FPGA based big data devices. Finally, just prior to joining Mentor, Bryan was a Senior Engineering Manager at Seagate doing SOC development for SSD controllers.|
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