|Conference:||DVCLUB Europe: November 2017|
|Speaker:||Abdel Ayari (Digital Design & Verification Solutions Applications Engineer) Mentor, A Siemens Business|
|Presentation Title:||How Formal Reduces Fault Analysis for ISO 26262 Safety Verification.|
|Abstract:||The ISO 26262 standard defines straightforward metrics for evaluating the “safeness” of a design by defining safety goals, safety mechanisms, and fault metrics. However, determining those metrics is difficult because evaluating every possible fault is impractical on the size of today’s designs. Formal verification tools have an advantage over other approaches because formal tools have the unique ability to trace cones of influence and eliminate large numbers of irrelevant faults in a process known as fault pruning. With a significantly reduced fault list, fault analysis can be performed exhaustively with formal techniques like sequential logic equivalency checking (SLEC), or coupled together with fault simulation and emulation for checking software based safety mechanisms. Formal tools provide unique capabilities that are essential for any automotive functional safety flow.
|Speaker Bio:||Abdelouahab Ayari, Ph.D. is an application engineer for formal verification, clock domain crossing, and low power verification. He received his doctor in formal verification at the University of Freiburg and worked for Micronas GmbH before joining Mentor, A Siemens Business. He has over 10 years’ experience on Assertion-Based Verification (ABV) and supporting major customers in the area of formal verification across Europe.|
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