DVClub Europe – October 2015 2017-05-18T09:29:56+00:00

Functional Safety in Hardware Verification

  • Meeting Date: Tuesday 20th October, 2015

The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events.  DVClub Europe attendance is free and is open to all non-service provider semiconductor professionals.

Presentation Downloads

Please select each session title to view the abstract and download/view the presentation slides.

Agenda (BST)

11.30Arrival and Networking
12.00Introduction, T&VS, Mike Bartley,  (CEO and Founder).
12.05Mentor Graphics, Nigel Elliot (Design and Verification Technologist).
Making your ISO 26262 Flow Flawless: Establishing Confidence in Verification Tools
12.25T&VS, Serrie Chapman (Requirements Engineering Consultant).
Safety, Requirements Engineering and Proof of Implementation
12:45Cadence, Adam Sherer (Product Management Group Director)
Unified Safety and Functional Verification
13.05Synopsys, Jean-Marc Forey (Verification Group/Corporate Application Engineer
Automotive Functional Safety Professional)
Designing Safer Cars – A Journey in ISO26262 Territories
13:25NXP Semiconductors, Haridas Vilakathara (Senior System Architect)
Realizing Road Vehicle SoC Solutions Based on ISO26262
13.45Close and Networking


  • Bristol: Broadcom, 910 Aztec West, Almondsbury, Bristol, BS32 4SR
  • Cambridge: ARM, 110 Fulbourn Road, Cambridge, CB1 9NJ
  • Grenoble: STMicroelectronics – Polygone Scientifique, 12 Rue Jules Horowitz, Grenoble
  • Sophia: Business Pôle, Entrée A, 1047, Route des Dolines, 06901 Sophia Antipolis Cedex
  • Remote Access


Registration is now closed.




The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.