|Conference:||Click here to see full programme|
|Presentation Title:||A model-based approach to software-driven Verification|
|Abstract:||The verification of electronic systems and subsystems is generally achieved today using software tests typically written in C. This practice allows exercising system use-cases from a programmer’s view, and creating real-life scenarios to test the system’s hardware and software layers.|
While prevalent and a fast growing practice, C tests creation is a manual and labor intensive effort that resembles the classic directed testing approach that was used for HW verification in the past. Combined with the complexity of writing the tests for systems and subsystems with multiple cores, many IPs, constrained resources, complex power control, coherent interconnect, and complex software controlled operations means that manual development of software driven tests barely scratches the surface of the full scenario space that each system/subsystem use case describes. Another prevalent need is to enable HW verification teams to run the same system scenarios early (often described as the “shift to the left” desire). A more focused testing effort and early identification of issues in phases that they can still easy to debug and fixed are some of the major benefit of introducing the programmer view to HW verification teams.
In this technical presentation, we will present a simplified yet representative SOC, and use a model-based approach to capture the legal scenario space in terms of it’s activities, resource availability, control flow and scheduling. After experiencing the modeling process, we will see how test writers with minimal knowledge of the system specifications, testbench knowledge, or the target implementation can easily create sophisticated, correct-by-construction scenarios. The same scenarios can be mapped to transaction-level coreless testbenches (e.g. UVM testbenches), or be ported to faster platforms like post-silicon, virtual platform and FPGA to achieve massive amount of quality content. Finally, coverage driven process can be used to achieve an automated, organized and predictable software driven test development that removes much of the compromises and risks of directed SW testing.
|Speaker Bio:||Sharon Rosenberg is a senior architect at Cadence. Sharon received his B.A. in computer science from Bar-Ilan University and joined Verisity Design in 1996 to lead the hardware testbench automation revolution. Sharon introduced many of the most used UVM concepts, including agents, factory, configuration mechanism, and sequences as the technical manager of the Cadence UVM team. Sharon represented Cadence in the Accellera UVM working group and co-authored the book A Practical Guide to Adopting the Universal Verification Methodology. Currently Sharon is driving software-driven methodology for SoC verification and represents Cadence in the Accellera Portable Stimulus Working Group.|
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