Software-Driven Verification Using UML Diagrams 2016-09-29T06:03:39+00:00
Conference:Click here to see full programme
Speaker:Adnan Hamid
Organisation:Breker Verification Systems
Presentation Title:Software-Driven Verification Using UML Diagrams
Abstract:Software-driven verification—generating test cases for an SoC’s embedded processors from graph-based models—is at the heart of the upcoming portable stimulus standard from Accellera. These test cases can be tuned to run on any verification platform: ESL models, RTL simulation, acceleration, emulation, FPGA prototypes, and silicon in the bring-up lab. The form and scope of the input model is a focus of the Accellera standardization effort and a key to a successful implementation of software-driven verification.

This talk considers a well-known existing modelling approach—UML diagrams—and considers how it might be used as part of the input specification for a software-driven verification tool. UML diagrams are a form of graph, so they are a natural candidate for such usage. The talk shows how UML diagrams can be used to specify verification intent, how they map easily to a standard C++ representation of the graph, and how existing drivers or other verification code can be incorporated.

In some test cases, the verification scenarios result in data being sent on or off chip, and the talk also covers how to synchronize the embedded code with activity on the SoC’s I/O ports. The test cases generated from the UML diagrams include not just stimulus, but also results checking, coverage, debug assistance, and performance metrics. The talk covers all of these topics to show how UML can be the front end to a complete solution for software-driven verification, covering the full scope of portable stimulus.

  • Software-driven verification required effective input models
  • The popular UML approach can be a key part of this input
  • It is possible to produce a complete solution starting with UML
Speaker Bio:Tom is Vice President of Marketing at Breker and Secretary of the Accellera Portable Stimulus Working Group. He has more than 15 years of experience in EDA verification applications and marketing. He has served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys, and Vice President of Applications Engineering at 0-In Design Automation. Before moving into EDA he was Vice President of Engineering at IP pioneer Virtual Chips. Tom has presented more than 100 conference talks, published more than 200 papers and articles, and contributed to 12 books. He holds a BS in Computer Systems Engineering from the University of Massachusetts at Amherst and an MS in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT).

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  • At the request of the speaker Presentation Slides will not be available post-event.
  • At the request of the speaker recording will not be available post-event.
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