| Conference: | Click here to see full programme |
| Speaker: | Adnan Hamid |
| Organisation: | Breker Verification Systems |
| Presentation Title: | Software-Driven Verification Using UML Diagrams |
| Abstract: | Software-driven verification—generating test cases for an SoC’s embedded processors from graph-based models—is at the heart of the upcoming portable stimulus standard from Accellera. These test cases can be tuned to run on any verification platform: ESL models, RTL simulation, acceleration, emulation, FPGA prototypes, and silicon in the bring-up lab. The form and scope of the input model is a focus of the Accellera standardization effort and a key to a successful implementation of software-driven verification.
This talk considers a well-known existing modelling approach—UML diagrams—and considers how it might be used as part of the input specification for a software-driven verification tool. UML diagrams are a form of graph, so they are a natural candidate for such usage. The talk shows how UML diagrams can be used to specify verification intent, how they map easily to a standard C++ representation of the graph, and how existing drivers or other verification code can be incorporated. In some test cases, the verification scenarios result in data being sent on or off chip, and the talk also covers how to synchronize the embedded code with activity on the SoC’s I/O ports. The test cases generated from the UML diagrams include not just stimulus, but also results checking, coverage, debug assistance, and performance metrics. The talk covers all of these topics to show how UML can be the front end to a complete solution for software-driven verification, covering the full scope of portable stimulus.
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