|Conference:||DVClub Europe – September 2015 (click here to see full programme)|
|Speaker:||Divyeshkumar Dhanjibhai Vora, Staff Design Engineer|
|Organisation:||ARM Embedded Technologies|
|Presentation Title:||Challenges with Power Aware Simulation and Verification Methodologies|
|Abstract:||PA simulation is a very powerful way to check the design power requirement early in the implementation cycle. However, PA simulation is still in early phase, and with increasing complexity, more check points need to be put in place to catch issues.This paper discusses about proposed enhancements like integrated PA models, liberty based assertions and UPF macro support using successive refinement, to fill the quality holes in the PA simulation flow. As the modelling complexity is increasing, it requires a thorough check to qualify the above said features in the library models.|
This paper also discusses a library based validation flow which has been developed in-house at ARM to ensure the qualification of the PA behaviour of each library cell against the reference vectors.
|Biography||Divyeshkumar is currently leading SC/IO Modelling group at ARM. Prior to ARM, he worked at STMicroelectronics in IO characterization group. He has been in this industry for more than 8 years. His area of interest is Physical IP Modeling and Low power flows. He has done presentation at different EDA forums on various topics pertaining to low power.|
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