Srobona Mitra, Synopsys India Pvt. Ltd.

Conference: DVClub Europe – September 2015 (click here to see full programme)
Speaker: Srobona Mitra, Senior R&D Engineer
Organisation: Synopsys India Pvt. Ltd.
Presentation Title: Static Power Intent Verification of Power State Switching Expressions
Abstract: Low power architecture of a design (specified in terms of UPF/CPF) goes through a series of refinements throughout the design cycle. Therefore it is very crucial to check whether the initial low power intent remains intact in these refinement steps. Any erroneous refinement step usually leads to functional bugs in the design, which can only be detected late in the verification cycle. In this paper, we propose a static checking methodology for verifying early that the power state switching expressions in a power architecture specification are equivalent through successive stages of power intent refinement.
Biography Srobona Mitra is currently Senior R&D Engineer in low power static verification tool development at Synopsys, Bangalore. Prior to this she has 3 years’ experience with the India Systems and Technology Laboratory, IBM India Pvt. Ltd., Bangalore, driving formal verification methodology deployment on System Z. She received her M.Tech. and Ph.D. degrees from the Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Kharagpur, Kharagpur, India, in 2006 and 2013, respectively.  She has authored several international conference and journal papers in the field of formal/semi-formal/static hardware verification.

View the Presentation Materials: