DVCLUB Europe – Feb 2017

Whatever your speciality, DVClub Europe provides an excellent opportunity for you to share your experiences, insights and knowledge on some of the key issues facing the design and verification industry. The next meeting will discuss:

Cache Coherency Verification with Formal, Portable Stimulus, and Multiple Platforms


  • Tuesday 7th February, 2017
  • Online, Bristol, Cambridge and Grenoble

The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events.

Attendance at DVClub Europe events is free and open to all non-service provider semiconductor professionals.

Agenda (GMT)

11.30 Arrival and Networking
12.00 Welcome and Introduction
– T&VS, Mike Bartley, (CEO and Founder)
12.05 A Multi-Tiered Approach to Verifying Cache Coherency
Tom Anderson, Cadence Design Systems.
– Download: Presentation Slides | Video Presentation
12.30 ARMv8 Cache Coherency Verification with TrekSoC Portable Stimulus Models
– Adnan Hamid, Breker Verification Systems.– Download: Presentation Slides | Video Presentation
12.55 Cache Coherency: The Next Big Problem in SoC Verification
– Robert Fredieu, Mentor Graphics
– Download: Presentation Slides | Video Presentation
13.20 Closing Remarks
13.25 Networking


  • Bristol: Imagination Technologies, 715 Aztec West, Almondsbury, Bristol, BS32 4UD, UK.
  • Cambridge: ARM, 110 Fulbourn Road, Cambridge, CB1 9NJ, UK
  • Grenoble: STMicroelectronics – Polygone Scientifique, 12 Rue Jules Horowitz, Grenoble, France
  • Remote Access


Now Closed




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