|Conference:||DVCLUB Europe: Cache Verification (Feb 2017)|
|Speaker:||Robert Fredieu (Verification Architect), Mentor Graphics|
|Presentation Title:||Cache Coherency: The Next Big Problem in SoC Verification|
|Abstract:||The details of cache coherency are and have been for many years a little known and poorly understood feature of computer systems. The complexity of a cache has always been limited by the ability to test it. The problem has now moved out of the domain of block level testing of the cache itself into a much more difficult problem of SoC verification.
As more IP becomes available from different sources that must use the same coherency protocol the need to understand both what must be tested and the results of testing becomes much more important. At the same time the ability to create a good test becomes much more difficult. Cache Coherency is intricately involved in the other big verification problems of ordering, performance, and arbitration. The trick is to do all this without requiring the verification team to become experts in the field.
|Speaker Bio:||Robert is a Verification Architect at Mentor Graphics focussed on new products in the SoC verification and design space. He has more than 36 years of experience in ASIC design and verification. Prior to Mentor he was a consultant working at AMD in SoC design and verification of gaming consoles and server products. Before AMD he worked as a consultant for many companies starting in design and later in the verification of computer systems, communication systems, test equipment, guidance systems, etc. He completed his first ASIC in 1981 and his most recent in 2013. Robert holds a BS in Physics from MIT and a BS in Electrical Engineering from MIT.|
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