|Conference:||DVCLUB Europe: Cache Verification (Feb 2017)|
|Speaker:||Tom Anderson (Director, Product Management) Cadence Design Systems|
|Presentation Title:||A Multi-Tiered Approach to Verifying Cache Coherency|
|Abstract:||SoC developers are facing a dilemma. As multiprocessor-based designs become more and more common, so do multi-level caches. The performance gains are well worth the silicon consumed, but cache coherency is widely regarded as one of the hardest feature to verify. This talk presents a multi-tiered methodology to address this challenge. Formal verification is used at the block and subsystem levels to verify the underlying cache coherency protocols. Automatically generated portable stimulus tests are run at the system level to ensure that no data is corrupted when all processors, caches, and memories interact. These tests can be tuned for maximum benefit in simulation, emulation, FPGA prototypes, and even silicon in the bring-up lab. This talk discusses the benefits at each stage.
|Speaker Bio:||Tom is a product management director in the System & Verification group at Cadence, focusing on portable stimulus, software-driven verification, and other technologies than span verification and validation platforms. He previously led the Cadence product management team for verification software products. Tom’s other former roles include Director of Technical Marketing at Synopsys, Vice President of Marketing at Breker Verification Systems, Vice President of Applications at 0-In Design Automation, and Vice President of Engineering at Virtual Chips. He is Secretary of the Accellera Portable Stimulus Working Group (PSWG) and has held leadership roles in many industry and standards groups. Tom holds a Master’s in Electrical Engineering and Computer Science from MIT and a BS in Computer Systems Engineering from the University of Massachusetts at Amherst.|
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