DVClub Europe – May 2018 : Formal Verification 2018-04-19T10:48:17+00:00

Formal Verification

DVClub Europe Meeting – May 15, 2018

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Event at a Glance

  • Tuesday 15th May, 2018

  • Lunchtime – 11:30 to 14:00 (GMT)

  • Online, Bristol, Cambridge and Grenoble

  • FREE to attend In-Person or Online

Formal Verification

Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis.  But success with Formal requires the effective selection and implementation of the right formal technologies and methods.  In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.

Agenda (GMT)

Time Session Description
11.30 Arrival and Networking
12.00 Welcome and Introduction
Mike Bartley, CEO and Founder, T&VS
12.05 Deep Formal Methodology for Arm Austin’s A-class CPUs: Evolution and Learnings
Vikram Khosa, Principal Engineer, Arm
12.30 Two Case Studies in Formal Deployment on ARM CPUs : Instruction-Fetch and Floating-Point Datapath
Vaibhav Agrawal, Principal Engineer, Arm
12.55 Presentation title to be confirmed
Speaker to be confirmed, OneSpin Solutions
13.10 It’s Been 24 Hours – Should I Kill My Formal Run?
Jeremy Levitt, Principal Engineer, Questa Formal R&D, Mentor, A Siemens Business
13.25 Closing Remarks
13.30 Networking

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

Sponsors

DVCLUB Europe is made possible through the generosity of our sponsors.

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Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
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