DVCLUB: IOT is IOMSLPT for Verification Engineers 2017-09-13T13:21:21+00:00
Conference:DVCLUB Europe: Sept 2017
Speaker:Adam Sherer (Product Management Group Director) Cadence Design Systems
Presentation Title:IOT is IOMSLPT for Verification Engineers – And an Acronym We’ll Never Use Again!
Abstract:IOT devices connect the analog world with the digital internet making them inherently dependent on both mixed signal and low power. Whether these devices are destine for mission critical applications consumer applications, the design parameters are drawing the analog and digital IP together with power management tighter than ever. Traditional methods of transistor-level verification remain necessary, but can’t simulate fast enough to run power-aware tests that enable functional verification. New methods binding SystemVerilog real number modeling (SVRNM) and IEEE 1801/UPF will be presented that can quickly and comprehensively verify IOT deveices.

  • IOT devices at the edge of the network are inherently mixed signal and low power
  • Traditional transistor-level verification is necessary but insufficient for IOT
  • New methods binding SystemVerilog real number modeling and IEEE1801/UPF are needed to quickly and comprehensively verify IOT devices
Speaker Bio:Adam Sherer and his team are responsible for the simulation-based verification technology product lifecycle management in the System Verification Group. His 26 years of experience in verification and software engineering include roles in product management, applications engineering, and R&D. Sherer is also the Chair of the Accellera Promotions Committee that provides marketing support for the Accellera Systems Initiative standards organization.

Sherer received his MS EE from the University of Rochester, with research published in the IEEE Transactions on CAD. His BS EE and BA CS were received from SUNY Buffalo. He also holds a 2017 patent in verification technology.

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