|Conference:||DVCLUB Europe: September 2017|
|Speaker:||Vireen Vodapalli, ARM Embedded Systems PVT Ltd|
|Presentation Title:||Co-Simulation for Functional Equivalence Checking|
|Abstract:||As a physical IP provider, ARM delivers frontend and backend views to our customers. It is very important to validate the views before they are delivered to our customers. As the frontend and backend views were developed independently, it is important to check if both the views are consistent to the functional specification. It will be effective if these views are verified against the same reference.
Verilog, being a simulation model, needs to mimic circuit behavior. For the Verilog and Spice to be functionally equivalent and inline with design specification, solutions using functional/logical equivalence tools were explored. Because of complex analog nature of Interface IP, tools could not handle this issue.
This presentation discusses methodology developed by Arm, in collaboration with EDA partner, to check the above views are matching the functional specification. Methodology is based on COSIM (co-simulation), where the same Verilog testbench is used in verifying Verilog & Spice views, using Cosimulator (verilog+spice). For each of the cells in the library, a Verilog testbench with exhaustive vectors is generated. Simulations are then run for both the views comparing simulated with expected output (0, 1 & HiZ) and an error is reported if the results do not match. This exhaustive verification is otherwise not feasible if a spice testbench has to be created. Currently infrastructure is deployed for Interface IP and can be extended for other Physical IP’s as well. This paper also discusses some of the aspects like handling transistors operating in the sub-threshold region and ESD devices for correct HiZ detection.
|Speaker Bio:||Vireen Vodapalli has 9 years of industry experience with the last 7 years working on modeling and methodology development for physical IP at ARM|
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