DVCLUB: Real Value Modeling for Improving the Verification Performance

Conference: DVCLUB Europe: September 2017
Speaker #1: Mallikarjuna Reddy, (Project Manager) Test and Verification Solutions
Speaker #2: Venkatramanarao (Member of Technical Staff – AMS Verification), Mindlance Technologies.
Presentation Title: Real Value Modeling for Improving the Verification Performance
Abstract: Due to increasing unpredictability and complexity of systems, circuit SPICE and Fast SPICE simulation cannot deliver verification closure on time. With the demand to have more functionality in today’s designs, the high performance SOC’s have to further accommodate Analog and Mixed Signal (AMS) designs. This leads to growing necessity of methodology for accurate and fast verification of AMS designs.

Here we are presenting AMS verification which uses well known Real Value Modelling (RVM) concepts. RVM processes floating-point real numbers like analog world, based on discrete events. The developed verification technique in this work makes it possible to behaviorally model analog effects such as supply ramp behavior, PVT variations, using event driven simulators and compatible with existing digital verification techniques.

Speaker Bio: Mallikarjuna has 14+ years of experience with Master’s degree from PSG college of technology. He has worked on Analog design, Analog modeling and AMS verification at Sub-system and Full-chip areas. He is currently working in Test and verification Solutions from last 3 years. In the past, he worked with Cypress semiconductors for about 11 years and a year in C2C solutions India Pvt Ltd.

Venkat has done Master’s Degree from Anna university.  He has 7 years of experience in AMS verification. He is interested to work on new methodologies in AMS verification, travelling, making friends and playing cricket.  He is currently working in Mindlance technologies. In the past, he worked with Applied Micro, Test and Verification and Cyient Ltd

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