Encapsulating Concurrent Assertions in UVM 2016-05-17T06:13:05+00:00
Conference:DVClub India – May 2016  (click here to see full programme)
Speaker:Surinder Sood
Organisation:SanDisk Corporation
Presentation Title:Encapsulating Concurrent Assertions in UVM
Abstract:IP/SOC checks are very important in any verification activity. But class-based system Verilog used in UVM does not allow concurrent assertions and, concurrent assertions are very important from all verification aspects. So to implement the concurrent assertions we require non class based object, like interfaces. This creates problems of encapsulation (since the verbose assertion code clutters the interface definition) and isolation (since the assertions depend on aspects of class configuration and operation).In this presentation, I’ll present some pragmatic approaches for encapsulation and operation of assertions including the mechanisms to make assertions aware of UVM Phases of the class-based environment.
Speaker Bio:Surinder Sood is a post graduate in microelectronics and currently working in SanDisk Corporation as a Staff engineer. I have an interest in SoC/IP Verification and trying to apply different ways and ideas in doing so. I have an overall experience of 12 years in verification.

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