DVClub India – November 2017
Unique Challenges in Verifying Automotive SoCs

Theme: Unique Challenges in Verifying Automotive SoCs

Event Date: Friday 24th November 2017 

Whatever your specialty, DVClub India provides an excellent opportunity for you to share your experiences, insights and knowledge on some of the key issues facing the design and verification industry.

We are now seeking submissions for presentations and papers describing interesting and innovative case-studies, technologies, tools, methodologies and architectures relating to:


Event Theme                     :               Unique Challenges in Verifying Automotive SoCs

Event Date                          :               24th November 2017 (In-Person and Online)

Event Time                         :               09:30 AM – 12:30 PM (IST)

Venue Details                    :               Cadence Design Systems – RMZ Eco World Road, Bengaluru, KA 560037, India – View Map



Eventbrite - DVCLUB India - November 2017


Key Submission Dates

Call for Papers Opens                     :               6th October 2017

Call for Papers Closes                     :               20th October 2017

Acceptance Notifications              :               23rd October 2017 (or before)

Final Presentations Required      :               27th October 2017


About DVClub

The principal goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. DVClub membership is free and is open to all non-service provider semiconductor professionals. For details of previous events click here.


DVClub India Accomplishments:

  • 6 DVClubs held successfully over the past three years in collaboration with Cadence
  • Wide variety of topics – ranging from UVM and Formal Verification to SoC Verification Challenges and Hardware-Software Co-verification
  • Many speakers from Tier 1 semiconductor companies
  • More than 150 participants


Submit Your Abstract

Abstracts should be targeted toward a technical audience of design and verification engineers. Abstract submissions should be no more than 2,500 characters and should include a short biography of the speaker. All abstracts will be reviewed and notice of acceptance will be sent via email. To submit your abstract please complete the form below:

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