Are we Ready for New set of Verification challenges posed by Automotive SoC’s

Conference: DVCLUB India: November 2017
Speaker: Lokesh Babu Pundreeka, Director , System Verification Group – Cadence Design Systems
Presentation Title: Are we Ready for New set of Verification challenges posed by Automotive SoC’s !!
Abstract: Autonomous driving is becoming real and it is demanding more safe and secure Electronic components (IC’s) for making autonomous vehicle are safety and reliable. Experience and learning from consumer and mobile ASIC’s design and verification may not enough to meet requirements for Automotive SoC’s. In this talk, we will explore some challenges in designing and verification of Automotive SoC’s and how we can overcome these challenges with cadence solutions.

  • Introduction to new set of challenges in verifying Automotive SoC’s
  • Bit more details about Safety and Security needs.
  • How cadence verification solutions are accelerating and minimizing risk of Automotive SoC’s verification.
Speaker Bio: Lokesh Babu is the Director of System Verification Group at Cadence, having 16+ years of experience in Mobile and Automotive ASIC’s design and verification. Started Career at Texas instruments (TI) as a Sr. Design Engineer and at TI worked on design and verification of High speed emulation chip and 802.11 a/b/g WIFI chips. In last 11+ year at cadence, driving System Verification Application Engineer team, primarily focused on new methodologies like Assertion based Formal Verification, UPF/CPF/1801 based Low power methodology, Automotive ISO26262 functional safety and security and Portable test and stimulus slandered (PSS).

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  • At the request of the speaker Presentation Slides will not be available post-event.
  • At the request of the speaker recording Slides will not be available post-event.