Fault Injection in Virtual Prototype – A Method to Increase SW Coverage 2018-02-01T12:05:09+00:00
Conference: DVCLUB India: November 2017
Speaker: Dineshkumar Selvaraj, Staff Engineer – Infineon Technologies
Presentation Title: Fault Injection in Virtual Prototype – A Method to Increase SW Coverage
Abstract: The complexity and safety aspects of Automotive applications are increasing day by day due to evolving ADAS market requirements. In addition it is mandatory for any automotive microcontroller to be compliant with ISO26262 standard and hence functional safety features form an integral part of each automotive product development phase, ranging from the specification, to design, implementation, integration, verification, validation, and production release. Any failure may lead to a serious impact both in terms of cost and life of a human being. A conventional testing technique often is not sufficient to cover all the corner case scenarios. This leads to challenges in achieving code coverage for safety critical SW. Fault injection technique is commonly used to overcome the above challenge.

In this presentation, different types of fault injection, VP based fault injection techniques and some use cases are described.

  • Functional Safety
  • Fault injection
  • Virtual Prototype
Speaker Bio: Dinesh is currently leading the Virtual prototype development of AURIX family of Microcontrollers in Infineon Technologies. He has got 13+ years of experience in ESL domain with focus into development of VP for classical pre silicon SW validation, RTL co-simulation and also early performance analysis and optimization using models. Prior to Infineon, he worked with Intel and Tata Elxsi. He pursued electrical engineering from NIT, Trichy.


View the Presentation Materials:

  • Presentation Slides
  • At the request of the speaker recording Slides will not be available post-event.
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.