|Name:||Doug Fisher (Verification AC Manager) , Jean-Marc Forey (Application Consultant)|
|Title:||Exploring Beyond the Limits of Formal Verification|
Abstract: Simulation is the basis for functional verification, with ever-improving effectiveness and efficiency via advances in methodology (UVM) and new technologies.
However, today’s SoCs have verification challenges that are impractical for simulation. For example, coherent bus-based systems may expand into essentially infinite state-spaces, rendering exhaustive simulation-based methods impractical. In this case, and others which are just as computationally intractable or even worse, the use of static verification methods is growing rapidly. Formal verification plays a key role in the engineer’s static verification toolbox, but has faced traditional limitations in capacity, time-to-results and uncertainty of completeness as input designs, constraints and assertions grown in size and complexity.
In this presentation, Synopsys experts will explore some new areas where formal verification may effectively complement simulation, robustly manage design size and complexity, and accurately combine formal and simulation results. We’ll talk about using new lemma-based methods to formally verify equivalence of a high-level algorithm written in C with the RTL used for its implementation. We will also discuss tools employing both formal and simulation-based mutation analysis to provide a unique combined view of verification completeness.
We believe that formal verification will be increasingly essential in overall functional verification strategies. The topics we discuss today will be part of the new generation of formal technologies and tools that will be widely employed to verify advanced designs, up to and including at the full-chip/SoC level.
Doug Fisher, Synopsys : Doug Fisher has a BASc degree from the ‘University of Waterloo, Canada’ (1986). He has been an IC designer, an IC team manager and a senior FAE at Calmos Systems, Texas Instruments and Nortel Networks. He came to the UK in 2000 to work as an expat for Nortel Networks Photonics R&D. Since 2001 he has been a verification specialist at Synopsys UK where he has a Senior Staff Application Consultant and Digital Verification Team Leader role.
Jean-Marc Forey, Synopsys : Jean-Marc Forey has a degree from the ‘Ecole Nationale Supérieure de Physique de Strasbourg’ (1988). He has held hardware development positions in Thomson CSF, Matra Marconi Space, Philips TRT, and Hewlett-Packard. He has been Senior Verification Application Engineer for Synopsys, then application engineer director in Certess from 2005 until their acquisition by SpringSoft in 2009. Since then he has been Technical Marketing Manager for Certitude and continues as a Senior Corporate Applications Engineer for Certitude in Synopsys since the Springsoft acquisition.