|Title:||Adopting Formal Methods in the Verification of ARM Based CPU Subsystems|
The CPU team at STMicroelectronics (Bristol) recently investigated the use of formal methods to increase productivity and quality in the verification of ARM based CPU subsystems. We evaluated a formal tool (Jasper) at the unit, block and sub-system level for three designs and found a number of benefits in terms of effort saved and reusability. We developed constrained random equivalents to increase our confidence in the tool and to make direct comparisons between the approaches. This talk presents the results of our study and also highlights some of the pitfalls we encountered.
James Pascoe is a Microprocessor Architect at STMicroelectronics in Bristol, UK. James is currently the Project Manager for the functional verification of a range of ARM CPU subsystems that are targeted at mobile and consumer applications. James’ verification interests include the use of formal methods and optimising verification work-flows for efficiency. While at ST, James has also worked in the areas of Product Engineering, Processor Development and Security, both in hardware and software roles. Before joining ST, James was a Software Engineer for U4EA Technologies where he developed novel Quality of Service software for IP networking devices. Prior to U4EA, James was a Research Fellow at Emory University in Atlanta, GA where he developed a suite of semantically enhanced multicast communication primitives. James holds a first class BSc (hons) in Computer Science and a PhD in IP networking both from The University of Reading. In addition, James holds an MBA (with distinction) from The University of Warwick. James was made a chartered engineer in 2008.