|Title:||Leveraging Formal in an Integrated Verification Platform|
Abstract: One of the perennial challenges for formal verification has been integration with other verification methods. The currently popular “app” model of formal deployment has emphasized specialized niches where formal can solve specific verification problems. However, the next generation of formal solutions must broadly support accelerating verification closure by combining simulation, emulation, static structural analysis, and language linting with formal techniques in a common platform. Such a next-generation unified formal verification solution must also provide the performance, ease-of-use, and cross-domain debug required by companies to meet demanding SoC design- and verification productivity and efficiency requirements.
This talk will explore some of the challenges and opportunities of combining formal technologies and methodologies with other verification techniques. We discuss combining formal techniques with advanced static structural analysis to find bugs, reduce spurious results, and accelerate root cause determination. We will also examine new formal/simulation coverage metrics that can improve designers visibility and the precision of coverage closure. Finally we will look at how formal techniques can help debug issues detected by other verification approaches.
Biography: Dan has been working on formal verification methodology and deployment at Synopsys for 15 years. He currently leads a team developing advanced formal verification engines and helps direct the development of the unified verification platform described in this talk. Prior experience includes development of tools for simulation model creation, timing analysis, and re-targetable microcode compilation. Dan received the MSEE degree from Stanford University. Outside of work, Dan enjoys building and flying experimental aircraft.