|Designation:||Principal Verification Engineer|
|Title:||Formal Verification of SoC Register Maps|
Abstract: Today’s SoCs are built up of many IP and subsystems. The inability to properly control or receive status from these components can cause significant issues and even result in a dead chip. Unfortunately, issues around the control and status registers (CSRs) are fairly common and cannot typically be “fixed in software” as this is the layer that interacts with the software. Historically people have used simulation-based approaches to validate CSR functionality but these methods are insufficient as they are not fully exhaustive. Exhaustive verification of anSoC register map is one of the verification goals at Dialog.
Traditionally, verification has been done using directed tests issuing read and write cycles targeting the register to verify the register access policies and reset values, based on a functional description in the design documentation. While this approach can verify the register map to a certain degree, it is not exhaustive with regards to providing comprehensive data pattern and address aliasing testing capabilities. The effort required for a user to define all the possible permutations of data patterns and register accesses is simply prohibitive. Formal analysis addresses this verification challenge. Using an IPXACT description of the register map generated from the register documentation, assertions can be created automatically to verify the register access policies.
Using formal analysis to prove the assertions provides exhaustive verification, without the need for a testbench, with a typical turnaround time in the order of minutes or less per check. Additionally, since formal analysis can prove assertions independently of each other, compute farms can be leveraged to allow many assertions to be verified in parallel, greatly reducing total turnaround time. Debugging assertion failures from formal analysis is typically easier than with simulation approaches, since formal will automatically find the shortest path to the failure, and can provide a waveform counter-example showing the failure. The paper reviews the results of using this approach on Dialog designs, and specifically highlights problems that were missed by simulation but caught by this technique.
Biography: Steve Holloway is currently Principal Verification Engineer within the IP group of Dialog Semiconductor. He has led the verification of various large-scale consumer SoC projects and has 14 years experience of Hardware Verification Methodologies including eRM, OVM and UVM. Steve has previously worked for Doulos, NXP and Trident Microsystems.