|Conference:||Formal Verification 2015 (click here to see full programme)|
|Speaker:||Alex Orr, Principal Engineer – IC Design|
|Presentation Title:||My first 100 days in formal-land|
|Abstract:||With tens of years of experience with dynamic simulation from TLM to UVM I used formal techniques for the first time on my current project. Can this old verification dog learn new tricks? Is there gain for the pain and how much did it hurt? Will I be using it on my next project …
|Biography||Over 20 years experience in semiconductor design and verification, worked for picoChip, Audium, Gnodal and now Broadcom. Is human, makes mistakes, considers admitting this the first step in becoming a better verification engineer!|
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