|Conference:||Formal Verification 2015 (click here to see full programme)|
|Speaker:||Doug Fisher, Senior Staff Application Consultant|
|Presentation Title:||Alternative formal techniques to increase verification productivity|
|Abstract:||Formal verification techniques such as property checking and formal applications have become an important part of today’s verification methodology. Designers play an increasing role in verification, both because of the additional resource and, also, because of the cost effectiveness of finding bugs earlier in the design flow. As we look for greater increases in productivity, we need to look for optimal formal techniques to address the practical challenges of the entire design and verification team.This presentation considers how the practical challenges of design bring-up, rapid verification of iterative design refinement, root cause analysis and verification sign-off can be addressed with transactional equivalence checking, sequential equivalence checking and formal debug techniques.
|Biography||Doug Fisher is a Senior Staff Application Consultant for Synopsys. Doug has worked as an ASIC design engineer, team leader, and manager in the semiconductor and telecommunications industries. For the last 14 years he has helped customers adopt simulation, formal and static verification technologies. Doug has a BASc in Electrical Engineering from the University of Waterloo.|
- At the request of the speaker the Presentation Slides will not be available post-event.
- At the request of the speaker the recording will not be available post-event.
Formal Verification 2015 is made possible through the generous support of our sponsors.