FV2017: Coverage Reloaded: Signing Off Designs with Confidence 2017-09-07T11:57:02+00:00
Conference: Formal Verification 2017
Speaker: Dr Ashish Darbari, (Director, Product Management) OneSpin Solutions GmbH
Presentation Title: Coverage Reloaded: Signing Off Designs with Confidence
Abstract: We all want to sign-off our designs with confidence, but just how do you know when you’re finished with verification? You need a reliable method to determine when enough is enough. This is typically done by computing metrics to obtain a quantifiable model of design assurance. When you reach 100% , then the design is ready for tape-out. In simulation-based verification, a combination of structural and functional metrics has traditionally been employed; usually the two are separate, yielding structural and functional coverage. In formal verification, there is a wide range of techniques for obtaining sign-off, but several important issues need to be addressed to obtain a well-rounded complete solution:

  1. Is the coverage tool asking the right question?
  2. How easy is it to run coverage tool?
  3. Is it quick to run the tool?
  4. Is the coverage report meaningful?
  5. How easy is it to analyse the report?
  6. Is the report linked to the design?
  7. Does coverage help identify any bugs?
  8. Can coverage identify over-constraints in the test bench?

In a recent Verification Futures talk, I presented an outline of how OneSpin’s Quantify tool helps to address these issues and why it provides the most meaningful coverage solution on the market for formal verification. In this talk, I will provide a brief overview of the Quantify technology, followed by an example to illustrate how it can help designers and verification engineers to get continuous feedback on design quality, as well as identify bugs in designs and fish out over-constraints in verification testbench.

  • Coverage
  • Sign-off
  • Formal Verification
Speaker Bio: Dr Ashish Darbari is a Director of Product Management team at OneSpin. He has been working with formal verification for nearly 15 years in senior roles at leading engineering organizations, including Imagination Technologies (UK), General Motors R&D (India), ARM (UK) and Intel (USA). At Imagination, he founded and headed the Advanced Verification Methodology Group which deployed formal verification on 50+ projects in multiple business units, while training nearly 100 engineers. He currently holds 10 patents and has published over 20 papers. Dr Darbari is a Fellow of British Computing Society, Fellow of IETE, and a Senior Member of ACM and IEEE. He holds a Master’s & Diplom Informatik from TU Dresden, Germany and a Doctorate from Oxford University, UK. Since March 2015, he has been a “Royal Academy of Engineering Visiting Professor” at the University of Southampton.

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