FV2017: Porting and Verifying a pre-RTL Legacy Design2017-07-17T09:30:27+00:00
Conference:Formal Verification 2017
Speaker:Elchanan Rappaport (President), Gila Logic
Presentation Title:Porting and Verifying a pre-RTL Legacy Design
Abstract:A common task for logic development is porting legacy designs to new target devices and technologies.   Ideally, this can be achieved by maintaining fully-portable RTL.   As a fallback, we need to modify our design, and then re-verify our functionality to confirm that we haven’t broken anything.An extreme case, which we encountered, was a pre-RTL legacy design, for which neither a simulation testbench, nor a detailed functional description existed.   This was compounded by the original design containing many non-synthesizable artifacts.  We present a methodology developed for porting such a design.

  • Extracting a structural netlist from the original inconsistent EDIF
  • Writing behavioral RTL based on this netlist
  • Confirming cycle accurate equivalence using both Dynamic and Formal methods
Speaker Bio:Elchanan Rappaport is the founder of Gila Logic, Inc. He has 35 years of experience in both logic design and verification, including 7 years at IBM TJ Watson Research.
For the last 15 years he has focused on high-end formal verification projects and is a common speaker at formal conferences and events. His Formal Verification clients include ARM, Microsoft, MobilEye, Texas Instruments, and Intel.

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  • Video Presentation