|Conference:||Formal Verification 2017|
|Speaker:||Dr. Jeremy Levitt, (Principal Engineer in the Formal Verification) Mentor, A Siemens Business|
|Presentation Title:||Exhaustively Verify SEU Mitigation Techniques Using Formal Verification|
|Abstract:||This session will discuss how automated, formal-based Sequential Logic Equivalency Checking (SLEC) techniques can exhaustively verify the effectiveness of the Singe Event Upset (SEU) mitigation logic vs. transient/SEU events — as well as stuck-at and bridging faults. To illustrate this, a case study describing fault analysis of a Triple Modular Redundancy (TMR) element; including fault population reduction, fault injection, checking and classification, and collection of metrics. Finally, we will compare formal results and run time against those obtained using dynamic simulation techniques, and show how formal is able to minimize the analysis effort required.
|Speaker Bio:||Dr. Levitt is a Principal Engineer in the Formal Verification Group of Mentor, A Siemens Business. He oversees R&D with a focus on algorithm development. Jeremy earned his Ph.D in Electrical Engineering from Stanford in 1997, M.S. in 1993 and a B.A.Sc in Engineering Science from the University of Toronto in 1991.|
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