Speaker: Richard Anderson, MathWorks UK Ltd. 2015-07-17T10:51:04+00:00
Conference:Intelligent Testing 2015 (click here to see full programme)
Speaker:Richard Anderson, Senior Developer
Organisation:MathWorks UK Ltd.
Presentation Title:On-Target Testing in the Simulink Model-Based Design Environment
Abstract:An introduction to Model-Based Design and the benefits of dynamic verification and validation tools. Explore the use of processor-in-the-loop (PIL) to test automatically generated code on the target, re-using test cases and simulations. Use PIL to capture performance and coverage metrics. PIL is fully integrated into the Simulink simulation environment.

  • Introduction to Model-Based Design and automatic code generation
  • Use of processor-in-the-loop (PIL) for on-target testing
  • Use of Simulink simulation environment to exercise generated code in a production hardware environment
BiographyRichard Anderson is a Senior Developer at MathWorks working on the “in-the-loop” technologies.  He has worked at the MathWorks for 7 years, being in development for the last 3 years. Before that he was a Consultant in the area of automatic code generation.  Prior to that he worked for 10 years in the Automotive Industry.


Intelligent Testing is made possible through the generous support of our sponsors.


The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.