Bob Gardner, Imagination Technologies 2014-04-17T14:32:17+00:00



Name: Bob Gardner

Designation: Developer Technology Engineer, Imagination Technologies

Title: Multicore Architecture of PowerVR


This talk will explain the multicore nature of PowerVR GPU architecture, covering both Series 5/5XT and the latest Series 6 families. We will discuss the benefit of the multi-core and multi-cluster architectures; how it enables PowerVR GPUs to deliver unrivalled compute power per mm2 and per mW; and what this means to software engineers using chips powered by PowerVR GPUs.


Bob Gardner graduated as a Games Programmer from Teesside University, where his studies focused on real-time graphics and the use of artificial neural networks in games.  As a developer of the PowerVR Insider SDK he has delivered training materials and presentations relating to optimizing for and understanding PowerVR Graphics IP to some the biggest players in mobile and embedded systems. Bob works in the Developer technology team of Imagination, which provides and develops the industry’s leading mobile and embedded graphics SDK, and provides technical support to more than 33,000 members of the PowerVR Insider ecosystem.

Download Presentation Slide

<<Go to Speaker List Page>>

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.