Jeronimo Castrillon, RWTH 2014-04-17T14:32:17+00:00




Name: Jeronimo Castrillon

Designation: Chief Engineer, RWTH (ICE)

Title: MAPS – Easy Multicore Programming


Traditional compiler technology does not scale for Multi-Processor Systems on Chip (MPSoCs). For this reason, the MAPS framework has been developed at the Chair for Software for Systems on Silicon (SSS). The MAPS Compiler is a tool framework with an Eclipse-based IDE that eases programming of heterogeneous MPSoC architectures. It uses both sequential C and a C language extension for describing applications in the form of process networks. It includes not only automatic code generators for various backends including host execution and various commercial MPSoCs, but also optimizing algorithms for temporal and spatial task-to-processor mapping for embedded MPSoC platforms based on novel code analysis and profiling technologies. The compiler infrastructure is easily retargetable to new platforms and the output is partitioned C code that can be compiled by the native C compilers of the target processing elements.

The talk will present a general overview of the MAPS framework, an overview of latest results and additions as well as an outlook into future plans for the framework.


Jeronimo Castrillon received the electronics engineering degree from the Pontificia Bolivariana University in Colombia in 2004 and a master degree from the ALaRI Institute in Switzerland in 2006. Thereafter he joined the Institute for Communication Technologies and Embedded Systems (ICE) at the RWTH Aachen University, where he is working as a full time researcher while pursuing his PhD. Since mid 2009, he is the chief engineer of the chair for Software for Systems on Silicon of the ICE institute.  His research interests lie on MPSoC programming: automatic code partitioning, code generation from abstract parallel programming models, compile time mapping and scheduling as well as HW/SW support for run-time systems.

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