Test and Verification Solutions Ltd

Name:Suleiman Abu Kharmeh
Designation: Verification Consultant
Title :Dynamic Verification of Low Power Design Intent

Abstract   :  Designs today include a complex set of power reduction techniques. These techniques are increasingly making their way from the system level down to lower level design entities including IP and block level of an electronic design. These low power techniques have associated functional aspects that must be included in the functional description of the design. The related power scenarios are increasing the overall complexity of the design. Advanced methodologies and associated EDA support are needed to verify the power intent of a design. This presentation briefly addresses the verification requirements of low power design at IP level and discusses few methods and techniques to address those verification requirements.

Biography:  Suleiman Abu Kharmeh has a PhD in Computer and Electronics Engineering, part of the Microelectronics Research Group. Research activities involve the design of an overall verification framework for communication driven systems. It focuses on formal specification and model-checking of various functional and performance design requirements. He is now providing verification services on low power designs.

Verification Futures Conference Presentation